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SC660E
SMBus System Clock Buffer for Mobile Applications
Product Features
10 output buffers for high clock fanout applications Each output can be internally disabled for EMI and power consumption reduction. Separate power supply for each group of 2 clock outputs for mixed voltage application. < 250ps skew between output clocks. 28-pin SSOP package for minimum board space Single output Tristate pin for testability
Product Description
The device is a high fanout system clock distributor. Its primary application is to create the large quantity of clocks needed to support a wide range of clock loads that are referenced to a single existing clock. Loads of up to 30 pF are supported. Primary application of this component is where long traces are used to transport clocks from their generating devices to their loads. The creation of EMI and the degradation of waveform rise and fall times is greatly reduced by running a single reference clock trace to this device and then using it to regenerate the clock that drives shorter traces by using the SC660 to generate the clocks at the target devices EMI is therefore minimized and board real estate is saved.
Block Diagram
VDDB
Pin Configuration
SDRAM(0:1)
SDRAM(2:3)
SDRAM4 FIN SDRAM5 VDD
SDATA SCLOCK OE
I2C
SDRAM(6:7) SDRAM(8:9)
VDDB SDRAM0 SDRAM1 VSS VDDB SDRAM2 SDRAM3 VSS FIN VDDB SDRAM4 VSS VDD SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDDB SDRAM9 SDRAM8 VSS VDDB SDRAM7 SDRAM6 VSS OE VDDB SDRAM5 VSS VSS SCLOCK
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 1 of 8
SC660E
SMBus System Clock Buffer for Mobile Applications
Pin Description
PIN No. 9 2,3,6,7,1 1,18,22,2 3,26,27 20 Pin Name FIN SDRAM(0:9) PWR VDDB I/O I O TYPE PAD BUF1 Description This pin is connected to the input reference clock. This clock must be in the range of 10.0 to 100.0 Mhz. Low skew output clocks.
OE
-
I
PAD
14
SDATA
VDD
I/O
PAD
15 4, 8, 12, 16, 17, 21, 25 1, 5, 10, 19, 24, 28 13
SCLOCK VSS
VDD
I PWR
PAD -
Buffer Output Enable pin. This pin is low it is used to place all output clocks (CLK1:10) in a tri state condition. This feature facilitates in production board level testing to be easily implemented for the clocks that this device produces. Has internal pull-up resistor. Serial Data for SMBus control interface. This pin receives data streams from the SMBus bus and outputs an acknowledge for valid data. Serial Clock for SMBus control interface. Ground pins for clock output buffers. These pins must be returned to the same potential to reduce output clock skew. Power for output clock buffers.
VDDB
-
PWR
-
VDD
-
PWR
-
Pin for device core logic.
Maximum Ratings1
This device contains circuitry to protect the inputs against damage due to high static voltages or electric Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Operating Temperature: Maximum Power Supply: -0.3V 0.3V -65C to + 150C -40C to +85C 7V field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 2 of 8
SC660E
SMBus System Clock Buffer for Mobile Applications
2-Wire SMBus Control Interface
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Subaddressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2wire control interface allows each clock output to be individually enabled or disabled. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first. The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions. Previously set control registers are retained.
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2), two additional bytes must be sent: 1) "Command Code " byte, and 2) "Byte Count" byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledged. After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1, Byte2, ....) will be valid and acknowledged. Byte 0: Function Select Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0
@Pup 1 1 1 1 1 1 1 1
Pin# 7 6 3 2
Description reserved reserved reserved reserved SDRAM3 (Active = 1, Forced low = 0) SDRAM2 (Active = 1, Forced low = 0) SDRAM1 (Active = 1, Forced low = 0) SDRAM0 (Active = 1, Forced low = 0)
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 3 of 8
SC660E
SMBus System Clock Buffer for Mobile Applications
Serial Control Registers (Cont.)
Byte 1: Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 27 26 23 22 Description SDRAM9 (Active = 1, Forced low = 0) SDRAM8 (Active = 1, Forced low = 0) SDRAM7 (Active = 1, Forced low = 0) SDRAM6 (Active = 1, Forced low = 0) reserved reserved reserved reserved
Byte 2: Clock Register ( 1 = enable, 0 = Stopped )
Bit 7 6 5 4 3 2 1 0
@Pup 1 1 0 0 0 0 1 1
Pin# 18 11 -
Description SDRAM5 (Active = 1, Forced low = 0) SDRAM4 (Active = 1, Forced low = 0) Not Used Not Used Not Used Not Used Not Used Not Used
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 4 of 8
SC660E
SMBus System Clock Buffer for Mobile Applications
Electrical Characteristics
Characteristic Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 40mA Output High Voltage IOH = 30mA Tri-State leakage Current Dynamic Supply Current Idd100 Static Supply Current Short Circuit Current Input Rise Time Isdd ISC TIR 25 2.4 220 4 mA mA mA nS Symbol VIL VIH IIL IIH VOL VOH Ioz Idd66 2.4 Min 2.0 -66 66 0.4 10 160 Typ Max 0.8 Units Vdc Vdc A A Vdc Vdc A mA Input frequency = 66 Mhz - All outputs on and at 30 pF load Input frequency 100 Mhz - All outputs on and at 30 pF load All outputs disabled no input clock 1 output at a time - 30 seconds .8 to 2.4 volts All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) Conditions -
VDD = VDD1 thru VDD5 =3.3V 5%, , TA = -40C to +85C
Switching Characteristics
Characteristic Output Duty Cycle Buffer out/out Skew All Buffer Outputs Buffer input to output Skew Jitter Cycle to Cycle* Jitter Absolute (Peak to Peak)* Symbol tSKEW tSKEW TJCC TJabs Min 45 2.0 Typ 50 4.0 Max 55 250 5.0 50 150 Units % pS nS pS pS @ 35 pF loading @ 35 pF loading Conditions Measured at 1.5V (50/50 in) 35 pF Load Measured at 1.5V
VDD = VDD1 thru VDD5 = 3.3V 5%, , TA = -40C to +85C *This jitter is additive to the input clock's jitter.
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 5 of 8
SC660E
SMBus System Clock Buffer for Mobile Applications
TB40_ Type Buffer Characteristics (All Clock Outputs)
Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Dynamic Output Impedance Rise/Fall Time Min Between 0.4 V and 2.4 V Rise/Fall Time Max Between 0.4 V and 2.4 V Symbol IOHmin IOHmax IOLmin IOLmax Zo TRFmin TRFmax Min 30 75 30 75 8 Typ Max 39 109 40 103 15 1.33 1.33 Units mA mA mA mA Ohms nS nS Conditions Vout = VDD - .5V Vout = 1.5V Vout = 0.4 Vout = 1.2V 66 and 100 MHz 30 pF Load 30 pF Load
VDD = VDD1 thru VDD5 =3.3V 5%, , TA = -40C to +85C
Package Drawing and Dimensions 28 Pin SSOP Outline Dimensions
INCHES C L A1 E H A2 B C D A2 A1 B e A D
a
MILLIMETERS MAX 0.079 0.006 0.073 0.015 0.010 0.413 0.220 MIN 0.05 1.65 0.22 0.09 9.90 5.00 NOM 1.75 10.20 5.30 0.65 BSC 0.323 0.037 8 7.40 0.55 0 7.80 0.75 8.20 0.95 8 MAX 2.0 0.15 1.85 0.38 0.25 10.50 5.60
SYMBOL A
MIN 0.002 0.065 0.009 0.004 0.390 0.197
NOM 0.069 0.402 0.209 0.026 BSC
E e H L a
0.291 0.022 0
0.307 0.030 -
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 6 of 8
SC660E
SMBus System Clock Buffer for Mobile Applications
Ordering Information
Part Number SC660EYB Package Type 28 PIN SSOP Production Flow Commercial, -40C to +85C
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. IMI SC660EYB Date Code, Lot #
Marking: Example:
SC660EYB Flow B = Commercial, -40C to + 85C Package Y = SSOP Revision Device Number
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications.
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 7 of 8
SC660E
SMBus System Clock Buffer for Mobile Applications
Document Title: SC660E SMBus System Clock Buffer for Mobile Applications Document Number: 38-07025
Rev. ** *A
ECN No. 106953 122723
Issue Date 06/14/01 12/17/02
Orig. of Change IKA RBI
Description of Change Convert from IMI to Cypress Added power-up requirements to maximum ratings information.
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134. Tel: 408-043-2600 http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002 Page 8 of 8

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